Sequences encapsulate user-defined procedures that generate multiple uvm_sequence_item-based transactions. Such sequences can be reused, extended, randomized, and combined sequentially and hierarchically in interesting ways to produce realistic stimulus to your DUT.
With uvm_sequence objects, users can encapsulate DUT initialization code, bus-based stress tests, network protocol stacks-- anything procedural-- then have them all execute in specific or random order to more quickly reach corner cases and coverage goals.
The UVM sequence item and sequence class hierarchy is shown below.
The base class for user-defined sequence items and also the base class for the uvm_sequence class.
class uvm_sequence_item extends uvm_transaction
The uvm_sequence class provides the interfaces necessary in order to create streams of sequence items and/or other sequences.
virtual class uvm_sequence #( type REQ = uvm_sequence_item, type RSP = REQ ) extends uvm_sequence_base